One double data rate (DDR) synchronous dynamic random access memory (SDRAM) system uses strobe signals to help transmit data between a memory controller and one or more DDR SDRAM memory modules mounted on a printed circuit board. For memory read operations, a DDR SDRAM memory module transmits a strobe signal along with associated data signals to the memory controller which then uses the strobe signal to latch the data signals. For memory write operations, the memory controller similarly transmits a strobe signal along with associated data signals to a DDR SDRAM memory module which then uses the strobe signal to latch the data signals.
Because the strobe signal should be delayed by ¼ phase relative to its associated data signals to help ensure the data signals are timely latched and because the DDR SDRAM memory module(s) do not delay the strobe signal for either memory read or write operations, the trace in the printed circuit board for the strobe signal route is extended to provide this delay for both memory read and write operations.
The length of trace to provide this delay, however, is a function of the clock frequency at which the strobe signal and its associated data signals are driven. Because the DDR SDRAM system on a given printed circuit board may be driven in only a specific frequency range, supporting other frequencies involves a printed circuit board design change. Extending the strobe signal route may also pose problems for printed circuit board designers as the length of trace to provide this delay may be excessively long.
Instead of extending the strobe signal route trace, the memory controller may comprise a delay circuit to delay the strobe signal in writing data to a DDR SDRAM memory module and in reading data from a DDR SDRAM memory module. The delay provided by the memory controller for memory reads, however, may vary from ¼ of the phase of the strobe signal from the DDR SDRAM memory module due to, for example, variations in process, variations in supply voltage, and/or variations in temperature of the memory controller and/or the DDR SDRAM memory module. This strobe delay variation due to such process, voltage, and/or temperature (PVT) variations may in turn limit the clock frequency at which the data signals may be driven and timely latched by the memory controller with adequate reliability.